How brachiopods get covered with nanometric silicon chips

Nanoslits in silicon chips.

Potassium hydroxide (KOH) etching of a patterned [100] oriented silicon wafer produces V-shaped etch pits. We demonstrate that the remaining thickness of silicon at the tip of the etch pit can be reduced to approximately 5 microm using an appropriately sized etch mask and optical feedback. Starting from such an etched chip, we have developed two different routes for fabricating 100 nm scale sli...

Heat generation in silicon nanometric semiconductor devices

In nano-devices the presence of very high and rapidly varying electric fields is the cause of thermal heating of the carriers and the crystal lattice. In fact, the external electric field transfers energy to the electrons and in turn to the lattice through the scattering mechanism. This self-heating process can influence significantly the electrical behaviour because the dissipated electrical e...

Vision Chips or Seeing Silicon

Asynchronous Design Methods for Dark Silicon Chips

The scaling of CMOS technologies continues to enable each two years more and more transistors to the ASIC designers and eventually application users. In theory this would mean that the processing architectures could also exponentially develop in the direction of further many-processor systems scaling. Nevertheless there are significant issues which may disable such scenario with the current (20...

Ultra-thin Silicon Chips in Flexible Microsystems

With the growing demand for mechanically flexible electrical systems and the increasing level of integration of electrical assemblies, hybrid build-ups combining polymer substrates and ultra-thin flexible silicon chips (system-in-foil) are getting more and more important. These systems need thin chips which maintain their functionality even in bent condition as well as reliable handling and ass...